The subject application claims benefit of the earlier filing dates of Japanese Patent Application Nos. Hei 11-345426 and 2000-12107 filed on Dec. 3, 1999 and Jan. 20, 2000 under the Paris Convention, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to semiconductor devices such as MISFETs (metal insulator semiconductor field-effect transistors) capable of suppressing threshold voltage (Vth) variations due to a short channel effect or manufacturing variations. In particular, the present invention relates to MISFETs"" impurity concentration profiles including channel impurity concentration profiles and counter impurity concentration profiles.
2. Description of the Related Art
It has been warned that micronization of a MISFET increases the influence of channel impurity concentration variations on Vth variations, to deteriorate the characteristics of the MISFET.
A CMOS (complementary metal oxide semiconductor) circuit may have a pMOSFET with an n+ polysilicon gate and a counter-doped channel surface. The counter-doped channel surface has an opposite conductivity type from a channel conductivity type, thereby forming a buried channel. The buried channel will suffer from a short channel effect if the counter-doped channel surface is deep. The short channel effect is a phenomenon that a threshold voltage (Vth) drops as a gate length is shortened. When micronized, the pMOSFET must have a short gate length. If the gate length is shortened to a lithography control limit, a gate length variation will account for a significant part of the gate length and the short channel effect will vary the electric characteristics of the pMOSFET, to deteriorate yield of CMOS circuits. A micronized CMOS circuit must employ a low source voltage. To decrease source voltage, it is necessary to decrease the threshold voltage (Vth) of a transistor. The threshold voltage, however, increases in proportion to a substrate impurity concentration, which must be high to suppress the short channel effect. Namely, increasing a substrate impurity concentration to suppress the short channel effect results in deteriorating transistor characteristics.
To solve this problem, a counter-doped layer of high impurity concentration may be formed at the surface of a substrate. This may increase a substrate impurity concentration to suppress the short channel effect. The counter-doped layer of high impurity concentration, however, must be very shallow to provide a low Vth value. It is difficult to form such a shallow, high-impurity-concentration, counter-doped layer because the counter-doped layer is inevitably thickened by thermal impurity diffusion during high-temperature processes such as a gate insulating film forming process and an impurity activation process.
As mentioned above, a buried channel is formed when a channel impurity layer is counter-doped. For example, an n-type impurity distribution having a gentle concentration profile is formed in a substrate, and p-type impurities are introduced into a shallow area of the substrate to cancel the n-type impurity distribution at the substrate surface, as disclosed by I. C. Kizilyalli et al. in xe2x80x9cN+-Polysilicon Gate PMOSFETs with Indium Doped Buried-Channels,xe2x80x9d IEEE Electron Device Letters, vol. 17, pp 46-49, 1996. This technique introduces p-type counter impurities to form a shallow p-type region in a substrate. Compared with a deep profile, the shallow profile forms a channel closer to the substrate surface, to prevent an increase in the effective thickness of a gate insulating film and suppress the short channel effect. To cancel a high n-type impurity concentration around a pn junction, the p-type impurities to be introduced must be of high concentration. MOSFETs with buried channels and n+ polysilicon gates are known to involve large Vth variations.
To meet a low source voltage, nMOSFETs as well as pMOSFETs are required to have low Vth values. A low Vth value is achievable by counter doping even if a channel impurity concentration is high. MOSFETs conventionally employ polysilicon gates that involve high gate resistance to hinder micronization. The gate resistance is reducible by replacing the polysilicon gates with metal gates. The metal gates provide a high work function, and therefore, an nMOSFET having a metal gate and a buried channel will simultaneously realize a low Vth value and a high channel impurity concentration to suppress the short channel effect, as disclosed by A. Chatterjee et al. in xe2x80x9cCMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator,xe2x80x9d IEDM 98, pp 777-780, 1998. However, there are no reports that describe how to realize a low Vth value with a metal gate. It is even claimed that a surface channel is superior to a buried channel for a metal gate because the buried channel involves large Vth variations. Namely, a large problem with the metal gate is a channel impurity concentration profile.
As mentioned above, buried-channel MOSFETs involve large Vth variations, and the cause of such Vth variations has been unclear. The inventors clarify the cause as follows.
FIG. 1 is a model showing a typical impurity concentration profile in a semiconductor substrate under a gate oxide film of an nMOSFET having a buried channel. A horizontal axis represents depths from an interface between the gate oxide film and the surface of the substrate. A vertical axis represents impurity concentrations. A channel impurity concentration profile 1 represents a p+ region containing channel impurities and is high and unchanged from the substrate surface to the inner part of the substrate. A counter impurity concentration profile 2 represents a counter-doped n+ impurity layer whose conductivity type is opposite to the conductivity type of the channel impurity region. The counter profile 2 extends from the substrate surface to a depth of 10 nm. The counter profile 2 is higher than the channel profile 1 and is unchanged. Based on these profiles 1 and 2, Vth variations will be simulated.
FIG. 2 is a graph showing simulation results on typical buried channel structures. The graph shows counter impurity concentrations and corresponding threshold voltage (Vth) values, as well as counter impurity concentration variations and corresponding Vth variations. The simulations are based on a source voltage of 1 V and a drain electrode receiving 1 V to measure each Vth value. The channel impurity concentration profile 1 of FIG. 1 has a concentration of 2xc3x971018 cmxe2x88x923. In FIG. 2, an abscissa represents counter impurity concentrations and an ordinate Vth values and Vth variations due to variations in the counter impurity concentration profile 2 of FIG. 1. A curve with xe2x80x9c+xe2x80x9d marks indicates Vth values. A curve with squares indicates Vth variations when the counter profile 2 of 10 nm deep is made shallower by 0.5 nm to 9.5 nm. A curve with xe2x80x9cxcex94xe2x80x9d marks indicates Vth variations when the impurity concentration of the counter profile 2 is reduced by 2%. These depth and concentration variations were selected to correspond to actual semiconductor device manufacturing variations. In FIG. 2, a low Vth value of 0.4 V is achievable with an increased counter impurity concentration of 5.3xc3x971018 cmxe2x88x923. At this concentration, the 0.5-nm-deep variation curve indicates a Vth variation of 50 mV, and the 2%-concentration variation curve indicates a Vth variation of 10 mV.
The cause of such variations will be studied in connection with an nMISFET.
A threshold voltage Vth of the MISFET is determined by a net impurity concentration profile irrespective of a channel impurity concentration profile or a counter impurity concentration profile. The net profile is a profile of net impurity concentrations, and each net impurity concentration is the absolute value of a difference between a p-type impurity concentration and an n-type impurity concentration at a given location. An impurity concentration is the concentration of electrically active impurities. Namely, an impurity concentration is an active impurity concentration and is not equal to a chemical concentration of impurity atoms. Generally, impurities introduced into a semiconductor to act as p- or n-type impurities have an electric activation ratio that is dependent on the kind and concentration of the impurities. Impurity concentrations referred in this specification are not chemical concentrations but are active concentrations representing electrically active impurities. Accordingly, the absolute value of an impurity concentration difference corresponds to a p-type impurity concentration if p-type impurities exceed n-type impurities and an n-type impurity concentration if n-type impurities exceed p-type impurities. This is because the charge of n-type impurities and the charge of p-type impurities of the same concentration cancel each other. When a transistor starts to operate in response to a gate bias, a depletion layer grows toward the inner part of a substrate in which the transistor is formed. The depletion layer produces space charge due to net impurities therein, to form an electric field that determines the operation of the transistor. As the depletion layer expands, carriers (holes) are driven toward the inner part of the substrate. In the depletion layer, part of the space charge that is not canceled by the charge of carriers (electrons or holes) helps form a channel electric field. The depletion layer is defined as a region where a carrier concentration is smaller than an impurity concentration by 10% or more.
To suppress the short channel effect, the depletion layer must stay around the substrate surface. To achieve this, the concentration of channel impurities must be high, and to cancel the high channel impurity concentration at the substrate surface, it is necessary to introduce counter impurities at high concentration. This is the reason why the counter impurity concentration profile 2 of FIG. 1 is high. Variations in the height or depth of the counter profile 2 vary the position of a pn junction or a net p-type impurity concentration profile around the pn junction. The channel impurity concentration profile 1 of FIG. 1 is also high, and therefore, variations in the channel profile 1 vary the pn junction position or a net n-type impurity concentration profile around the pn junction. In this way, the larger the channel and counter impurity concentration variations, the greater the variations in a net impurity concentration profile around a pn junction. The net impurity concentration profile determines a Vth value. If one of the p- and n-type impurity concentration profiles varies, a net impurity profile varies to change a Vth value. A buried-channel transistor more easily varies its Vth than a surface-channel transistor because the surface-channel transistor determines Vth according to a single impurity concentration profile while the buried-channel transistor determines Vth according to two impurity concentration profiles. Namely, the buried-channel transistor easily changes its channel structure due to variations in the net impurity concentration profile thereof.
The problem mentioned above is common to every transistor having a pn junction in a channel. Namely, the problem occurs on a surface-channel transistor that is formed by introducing n-type impurities into a shallow depth or at a low concentration, or by controlling the work function of gate electrode material, or by applying a substrate bias. The problem also occurs on a transistor whose channel is intermediate between the surface-channel transistor and the buried-channel transistor.
Generally, a gate electrode made of metal or metal compound has a work function in the middle of a silicon band gap. This configuration tends to increase a threshold voltage Vth in a MISFET. To drop Vth for micronization of a MISFET, a buried channel is used as mentioned above. The buried channel, however, varies Vth to deteriorate yield of micronized ICs. To provide a metal gate without a buried channel, metal having a work function at an end of the silicon band gap is effective. When employing such metal for gate electrodes, an nMISFET and a pMISFET in a CMOS circuit must be made of different metal materials (dual gates), to complicate manufacturing processes and increase costs. In this way, micronization of metal gate MISFETs for a CMOS circuit involves a difficult task of finding a proper combination of work functions and channel profiles.
An object of the present invention is to provide a semiconductor device capable of suppressing Vth variations against the short channel effect or manufacturing variations.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing Vth variations against the short channel effect or manufacturing variations.
Impurity concentration profiles that cause little Vth variations found by the inventors will be explained.
Based on the fact that overlapping p- and n-type impurity concentration profiles one another increases Vth variations, the inventors tried to find an optimum channel impurity concentration profile that reduces Vth variations.
FIG. 3 is a model showing a channel impurity concentration profile in a semiconductor substrate under a gate oxide film of a surface channel nMOSFET. A horizontal axis represents distances from an interface between the gate oxide film and the surface of the substrate, and a vertical axis represents channel impurity concentrations. First, it is assumed that a p+ region of high impurity concentration constantly extends to the inner part of the substrate. In this case, a segment 4 and a dotted line 3 define a channel impurity concentration profile. As the nMOSFET is micronized, the threshold voltage Vth thereof increasingly varies due to the short channel effect. The short channel effect is suppressible by thinning the gate insulating film and by increasing the concentration of substrate impurities. The short channel effect is also suppressible by reducing the depth of a source or drain, in particular the drain, or both. In this example, the source-drain structure is unchanged, i.e., the depth of a source-drain layer junction is fixed to 35 nm, to study the influence of channel impurities on the short channel effect. For micronization, power consumption must be minimized, a source voltage must be dropped, and Vth must be decreased. To decrease Vth, the concentration of impurities at the substrate surface must be lowered. To achieve this, the dotted line 3 of the channel impurity concentration profile 1 is replaced with segments 5 and 6, to form a stepped channel impurity concentration profile. At the same time, the channel profile 1 may be changed to have a dotted line 7 because the short channel effect is suppressible if the segment 4 has a specified length.
To evaluate Vth variations with the stepped channel impurity concentration profile 1, the short channel effect that directly influences Vth variations must be quantized. FIG. 4 is a graph showing Vth variations with respect to gate length (L) variations. An abscissa represents gate lengths and an ordinate represents Vth values. A curve 8 represents gate lengths and corresponding Vth values. The shorter the gate length, the smaller the Vth value. This is the short channel effect. The shorter the gate length, the larger the inclination of the curve 8. This inclination of the curve 8 is considered to indicate the magnitude of the short channel effect. To evaluate the inclination of the curve 8, the inventors worked out an SCE (short channel effect) range as follows:
(SCE range:L)=Vth(L+8%)xe2x88x92Vth(Lxe2x88x928%)xe2x80x83xe2x80x83(1) 
where L is an optional gate length, L+8% is a gate length longer than L by +8%, Vth(L+8%) is a threshold voltage at L+8%, Lxe2x88x928% is a gate length shorter than L by 8%, and Vth(Lxe2x88x928%) is a threshold voltage at Lxe2x88x928%. The value of 8% in the expression (1) is optional and may be set in the range of gate length variations to be caused in MOSFET manufacturing processes, to evaluate Vth variations caused by manufacturing variations.
Effectiveness of the SCE ranges in evaluating the magnitude of the short channel effect will be studied according to the graph of FIG. 4. A gate length L1 corresponds to an SCE range R1 on the Vth axis, and a gate length L2 corresponds to an SCE range R2. The SCE range R2 is greater than the SCE range R1, and therefore, it is concluded that the SCE ranges are capable of quantizing the short channel effect. The curve 8 is alterable to a dotted line 9 or 10 by changing a corresponding impurity concentration profile. Namely, an impurity concentration profile that provides a minimum SCE range with respect to a given gate length (for example, L2) is a required impurity concentration profile. Vth variations caused by channel impurity variations are dependent on the structure of a channel. Vth variations in a transistor having a pn junction in a channel are dependent on a Vth value that is determined by gate material and a channel impurity concentration profile.
FIG. 5 is a graph showing Vth values and SCE ranges with respect to distances (the depths of the segment 5 in FIG. 3) from the surface of a semiconductor substrate to the step of a stepped impurity concentration profile (FIG. 3) in a metal-gate transistor. Values on the graph are based on simulations. The simulations were carried out on assumptions that the segment 4 of FIG. 3 corresponds to an impurity concentration of 5xc3x971018 cmxe2x88x923, the segment 6 of FIG. 3 corresponds to an impurity concentration of 1xc3x971017 cmxe2x88x923, and a gate length of 95 nm. In FIG. 5, an abscissa represents distances from the substrate surface to the step (the segment 5 of FIG. 3), and an ordinate represents Vth values and SCE ranges. A curve with squares indicates Vth values, and a curve with xe2x80x9cxcex94xe2x80x9d marks indicates SCE ranges. It is understood that the deeper the low-impurity-concentration surface layer, the smaller the Vth value and larger the SCE range. A Vth value of 0.4 V is attained at a depth of 50 nm and an SCE range of 70 mV. The Vth curve at the depth of 50 nm shows that the Vth value will vary by 14 mV if the depth is reduced by 2.5 nm to 47.5 nm. This variation of 14 mV is a third of the Vth variation of 50 mV of FIG. 2. When the level of the segment 6 of FIG. 3 is lowered below 1xc3x971017 cmxe2x88x923, no substantial change is observed in the simulation results of FIG. 5, except that Vth slightly decreases. Consequently, the stepped profile of FIG. 3 causes smaller Vth variations with respect to impurity concentration variations, compared with the profile of FIG. 1. The stepped profile of FIG. 3 is effective to reduce Vth variations with respect to impurity concentration variations. It is required to further reduce the SCE range of the stepped profile of FIG. 3.
To achieve this, a first aspect of the present invention provides a semiconductor device having a first semiconductor region formed in a semiconductor substrate and having a first conductivity type (for example, p-type) due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type (for example, n-type) due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region also contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of the concentration of the second-conductivity-type active impurities contained in the second semiconductor region. The semiconductor device further has an insulating film formed on the surface of the semiconductor substrate over the second semiconductor region, a conductor formed on the insulating film, a third semiconductor region of the second conductivity type formed at the surface of the semiconductor substrate in contact with a side face of the second semiconductor region, and a fourth semiconductor region of the second conductivity type formed at the surface of the semiconductor substrate in contact with a side face of the second semiconductor region.
The first aspect realizes a low impurity concentration at a junction area and at the substrate surface and a small difference between a net impurity concentration and a p- or n-type impurity concentration. This reduces the influence of p- or n-type impurity concentration variations on a net impurity concentration, thereby suppressing Vth variations. For a metal-gate transistor that must have a pn junction in a channel due to a high work function, the first aspect suppresses Vth variations. The impurity concentration profiles of the first aspect are producible with a damascene gate process. PMISFETs and nMISFETs having metal gates according to the first aspect are capable of forming high-performance semiconductor IC chips at high yield.
According to the first aspect, the concentration profile of the first-conductivity-type impurities in the first semiconductor region may steeply decrease toward the substrate surface and may include a part where a concentration ratio per 3 nm is smaller than 0.9. This secures a high p-type impurity concentration region, suppresses the short channel effect, reduces a difference between a net impurity concentration profile in the n-type impurity region and an n-type impurity concentration profile in the same region, and suppresses Vth variations.
According to the first aspect, the concentration of second-conductivity-type impurities at the bottom of the second semiconductor region may be smaller than half the maximum concentration of first-conductivity-type impurities contained in a depletion layer formed during the operation of the semiconductor device. This secures a high p-type impurity concentration area, suppresses the short channel effect, decreases the concentration of n-type impurities, reduces the location dependence of the n-type impurity profile to suppress n-type impurity variations, and suppresses net n- and p-type impurity profile variations to suppress Vth variations.
According to the first aspect, at the bottom of the second semiconductor region, a concentration gradient of the second-conductivity-type impurities is smaller than that of the first-conductivity-type impurities. This provides the same advantage mentioned above.
According to the first aspect, the concentration of second-conductivity-type impurities at the bottom of a depletion layer formed during the operation of the semiconductor device may be smaller than a quarter of the maximum concentration of the first-conductivity-type impurities in the depletion layer. This decreases the concentration of n-type impurities in a part of the p-type impurity region that determines the characteristics of the MISFET, reduces a difference between a net p-type profile and a p-type profile, and suppresses Vth variations.
According to the first aspect, a peak concentration of the second-conductivity-type impurities in the second semiconductor region is on the semiconductor substrate side of the second semiconductor region. This separates a main distribution of the second-conductivity-type (for example, n-type) impurities from the p-type impurities, reduces a difference between a net impurity concentration profile in the n-type region and an n-type-impurity concentration profile in the same region, and suppresses Vth variations.
According to the first aspect, the concentration of first-conductivity-type impurities may be smaller than half a peak concentration of second-conductivity-type impurities in the second semiconductor region at the peak concentration position of the second-conductivity-type impurities. For example, the concentration of p-type impurities is lower than half the concentration of n-type impurities at a peak of the n-type impurity concentration profile in the second semiconductor region, to decrease a difference between a net n-type impurity concentration profile and an n-type impurity concentration profile in the second semiconductor region to suppress Vth variations.
According to the first aspect, the concentration of first-conductivity-type impurities may be smaller than a quarter of the concentration of second-conductivity-type impurities at the substrate surface. For example, the concentration of p-type impurities at the substrate surface where Vth is strongly influenced by the p-type impurities is decreased below the concentration of n-type impurities. This reduces a difference between a net n-type impurity concentration profile and an n-type impurity concentration profile, to suppress Vth variations.
According to the first aspect, the concentration of second-conductivity-type impurities at the substrate surface may be smaller than two times the concentration of second-conductivity-type impurities at the bottom of the second semiconductor region, or smaller than two times a peak concentration of second-conductivity-type impurities in the second semiconductor region. At the same time, the concentration of second-conductivity-type impurities at the substrate surface may be greater than half the concentration of second-conductivity-type impurities at the bottom of the second semiconductor region. In this case, the second-conductivity-type (for example, n-type) impurities have a gentle concentration profile without localization. This suppresses n-type impurity variations, net n-type impurity variations, net p-type impurity variations, and Vth variations and makes the control of Vth values easier.
According to the first aspect, a concentration profile of the first-conductivity-type impurities in the first semiconductor region may sharply fall toward the substrate surface and may have a part where a concentration ratio per 1 nm is 0.9 or smaller. This secures a high-concentration area of first-conductivity-type (for example, p-type) impurities to suppress the short channel effect and reduces the concentration of n-type impurities to suppress Vth variations.
According to the first aspect, the first-conductivity-type impurities may be indium. When applied to nMISFETs, the indium provides a small diffusion coefficient to form a p-type impurity region.
According to the first aspect, the second-conductivity-type impurities may be phosphorus. The phosphorus has a large diffusion coefficient to form nMISFETs having a gentle n-type impurity concentration profile.
According to the first aspect, the second-conductivity-type impurities may be antimony or arsenic. The antimony has a small diffusion coefficient to form nMISFETs having a narrow n-type impurity concentration profile, which may reduce an overlap area with a p-type impurity concentration profile. This secures a sufficient net p-type impurity concentration to suppress the short channel effect and Vth variations.
According to the first aspect, the first-conductivity-type impurities may be antimony or arsenic. The antimony or arsenic has a small diffusion coefficient to form a proper n-type impurity concentration profile for pMISFETs.
According to the first aspect, the second-conductivity-type impurities may be boron. The boron has a large diffusion coefficient to form pMISFETs having a gentle p-type impurity concentration profile.
According to the first aspect, the second-conductivity-type impurities may be indium. The indium has a small diffusion coefficient to form a pMISFET having a narrow p-type impurity concentration profile.
According to the first aspect, the conductor may be made of metal or metal compound. This reduces the resistance of a gate electrode and reduces an increase in the effective thickness of a gate insulating film due to interface depletion. This prevents the short channel effect, realizes a low Vth value for a MISFET without Vth variations.
The semiconductor device of the first aspect with the first conductivity type being p and the semiconductor device of the first aspect with the first conductivity type being n may be formed on the same semiconductor substrate. This arrangement provides a metal-gate nMISFET and a metal-gate pMISFET of low gate resistance, no increase in the effective thickness of a gate insulating film, and little Vth variations. These semiconductor devices realize a high-performance, low-power-consumption, semiconductor IC chip.
The semiconductor device of the first aspect with the first conductivity type being p and the semiconductor device of the first aspect with the first conductivity type being n may have conductors made of the same metal or the same metal compound. Producing pMISFETs and nMISFETs having the same gate material simplifies production processes and reduces manufacturing costs.
A second aspect of the present invention provides a method of manufacturing a semiconductor device, including a first step of introducing first-conductivity-type impurities into first and second regions of a semiconductor substrate, the first region being in the vicinity of the surface of the semiconductor substrate, the second region being behind the first region away from the surface of the semiconductor substrate, a concentration profile of first-conductivity-type active impurities in the second region being at least four times higher than a concentration profile of first-conductivity-type active impurities in the first region, a second step of introducing second-conductivity-type impurities into the first region so that a concentration of second-conductivity-type active impurities in the first region is higher than a concentration of the first-conductivity-type active impurities in the first region, a third step of forming an insulating film on the surface of the semiconductor substrate, a fourth step of forming a conductor on the insulating film, and a fifth step of forming a semiconductor region of the second conductivity type on each side of the conductor in contact with the second region. The semiconductor device thus formed has steep or narrow impurity concentration profiles.
According to the second aspect, the fifth step may be carried out first. Thereafter, an opening for implanting impurities is formed, the first step is carried out to introduce the first-conductivity-type impurities into the substrate through the opening, and the third and fourth steps are carried out. This method employs the damascene gate process to form a gate electrode conductor, to minimize heat treatment on the channel impurities implanted in the first step and realize a steep impurity concentration profile.
According to the second aspect, the second step may be carried out after the formation of the opening. This reduces heat treatment on the counter impurities implanted in the second step, to produce a narrow impurity concentration profile.
According to the second aspect, the second step may be carried out before the fifth step. When manufacturing an nMISFET (or a pMISFET with inverted polarities) by the damascene gate process, counter impurities are doped first, and an n-type impurity region at the surface is smoothly distributed by heat treatment. Ion implantation for making a channel is carried out after heat treatment for activating source and drain impurities. This minimizes heat treatment on p-type impurities, to secure a steep p-type impurity concentration profile.
According to the second aspect, the insulating film may be formed by chemical vapor growing. This implants channel impurities, and then, forms a gate insulating film at a low temperature without thermal oxidation, to secure a steep or narrow channel impurity concentration profile.
According to the second aspect, no step carried out after the fourth step may maintain temperatures higher than 850 degrees centigrade for more than 60 seconds. This reduces high-temperature heat treatment, secures a steep or narrow channel impurity concentration profile, and makes the control of impurity concentrations easier.
A third aspect of the present invention provides a semiconductor device having a semiconductor base layer containing first conductive impurities, a semiconductor layer formed on the base layer and having a groove whose bottom is the surface of the base layer, an insulator layer for covering the bottom and side walls of the groove, and a conductor layer formed in the groove on the insulator layer.
The semiconductor layer contains second conductive impurities whose conductivity type is opposite to the conductivity type of the first conductive impurities. The surface of the base layer has an impurity diffusion layer containing the second conductive impurities whose concentration is lower than the concentration of those in the semiconductor layer. The semiconductor layer with the groove forms a pattern that is identical to a pattern formed by the impurity diffusion layer.
A fourth aspect of the present invention provides a method of manufacturing a semiconductor device including the steps of preparing a semiconductor base layer containing first conductive impurities and forming a semiconductor layer on the base layer, the semiconductor layer containing second conductive impurities whose conductivity type is opposite to that of the first conductive impurities, forming an impurity diffusion layer by diffusing part of the second conductive impurities contained in the semiconductor layer into the surface of the base layer, forming a groove in the semiconductor layer after the impurity diffusion layer forming step, the groove having a bottom that is the surface of the base layer, forming an insulator layer on the semiconductor layer, to cover the bottom and side walls of the groove and leave a space in the groove, and forming a conductor layer on the insulator layer to fill at least part of the space in the groove.
The impurity diffusion layer is formed by solid-phase-diffusing, the second conductive impurities contained in the semiconductor layer into the surface of the base layer, before forming the groove for the conductor layer. The impurity diffusion layer corresponds to conventional MISFET""s source and drain extensions and a counter dope layer for a buried channel. Namely, the impurity diffusion layer serves as the extensions and counter dope layer. Unlike the prior art that forms the counter dope layer separately from the extensions after the formation of a groove, the fourth aspect of the present invention maintains a constant contact state between a source-drain diffusion layer and a channel region. Compared with ion implantation, the solid-phase diffusion of the fourth aspect is easy to form a thin impurity diffusion layer. The fourth aspect, therefore, provides a metal gate MISFET capable of sufficiently suppressing the short channel effect, lowering a threshold voltage, and minimizing characteristic variations.
The fourth aspect forms the semiconductor layer and an element isolation film to surround the semiconductor layer. The second conductive impurities are solid-state-diffused into an element region surrounded by the element isolation film. When seen orthogonally to the principle plane of the base layer, the semiconductor layer and impurity diffusion layer are identical with the element region before the formation of the groove. Namely, the semiconductor layer pattern including the groove is identical with the impurity diffusion layer pattern.
The fourth aspect forms the impurity diffusion layer by solid-phase-diffusing the second impurities from the semiconductor layer into the surface of the base layer, so that the thickness and concentration of the impurity diffusion layer are uniform under the semiconductor layer and under the conductor layer. The fourth aspect not only makes the impurity diffusion layer pattern identical with the semiconductor layer pattern including the groove but also makes the thickness and impurity concentration of the impurity diffusion layer uniform.
The fourth aspect forms the insulator layer and conductor layer in the groove by successively filling at least part of the groove with the layers and by removing parts of the layers outside the groove by, for example, CMP. The element isolation film is used as a stopper for the CMP. Before the CMP, the top of the semiconductor layer may be flush with or higher than the top of the element isolation film, and the CMP puts them substantially in the same plane.
As mentioned above, the present invention provides a high-performance semiconductor device having micronized transistors that are resistive to impurity concentration variations caused by processing variations, and a method of manufacturing such a semiconductor device. The present invention also provides a metal-gate MISFET capable of suppressing the short channel effect with the use of impurity concentration profiles having a pn junction in a channel. The MISFET realizes a low Vth value and suppresses Vth variations caused by impurity concentration variations. The metal-gate MISFET is superior to a polysilicon-gate transistor in performance and is able to provide fine ICs at high yield.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.